Micro-path of SRAM below 3 nm in new device environment

As semiconductor technology continues to advance to smaller nodes,the gate length of transistors has approached the physical limit.In the process below 3 nm,how to maintain and improve the performance of devices,especially the performance of key circuits such as SRAM(Static Random Access Memory),has become an urgent problem for the industry.The extremely miniature gate length forces technicians to adjust the device architecture to enhance the electric field control ability of the channel region under the gate,thus improving the electrostatic characteristics of the device and ensuring that the channel can be effectively controlled in the off state.
 

Introduction and influence of FinFET architecture

As an important architectural innovation to meet the challenge of 20 nm node,FinFET device significantly improves the electrostatic integrity of the device.The vertical channel structure makes the effective width mainly determined by the fin height,which not only optimizes the utilization efficiency of the active region,but also further improves the integration density of the device through the fin spacing.FinFET is widely used in many process nodes because the fin spacing is usually less than twice the height of the device,and it achieves higher current driving capability per unit area.As the gate length is further reduced to below 20 nm,the electrostatic control ability of FinFET is gradually weakened.The distance between the source and the drain is shrinking,which intensifies the short channel effect and leads to the increase of leakage current,thus affecting the stability and energy efficiency of SRAM cells.Therefore,researchers began to explore more advanced device architecture of SRAM to continue the vitality of Moore's Law.
 

The rise of nanosheets and nanowire devices

In order to cope with the shortage of FinFET in more advanced nodes,the structure of full surround gate(GAA)has gradually become a research hotspot.This kind of structure includes nanosheets and nanowire devices,and their channels are completely wrapped by gates,thus achieving better electrostatic control.At the node below 3 nm,such devices show significant advantages,especially in suppressing short channel effect,which provides new possibilities for improving the performance of SRAM.With the shrinking size of logic devices,nano-chip architecture is gradually facing challenges in design rules.Especially in the design of active area,its miniaturization potential is limited and needs further optimization.
 

Exploration of New Device Architecture

In order to break through the bottleneck of nano-chip architecture,researchers have proposed a variety of new device schemes.Among them,the"worksheet"architecture is regarded as a natural extension of nanosheets.By optimizing the design of pn spacing,the key bottleneck in the current architecture is alleviated.In addition,the complementary field effect transistor(CFET)architecture achieves a very high device compactness by stacking nFET and pFET in the same structure,which provides a new direction for SRAM design in the future.CFET architecture can not only greatly improve the integration density of devices,but also help to further reduce power consumption and improve performance.With the process node moving below 3 nm,this new architecture is expected to play an important role in SRAM and other key circuits.
 

From FinFET to nano-chip,to new architectures such as CFET,semiconductor devices continue to break through technical bottlenecks in the process of miniaturization of nodes below 3 nanometers.These advances not only promote the continuous optimization of SRAM performance,but also lay a solid foundation for the development of the entire integrated circuit industry.In the future,with the introduction of new materials and technologies,the implementation path of SRAM in smaller nodes will be clearer,which will provide stronger support for applications such as high-performance computing and artificial intelligence.