SRAM faces 2D scaling bottleneck

In the field of semiconductor,"scaling"used to be the unchangeable golden rule,which meant making smaller,cheaper and more powerful chips with more sophisticated technology.However,this law is gradually failing in the core of memory-SRAM(Static Random Access Memory)and DRAM(Dynamic Random Access Memory).The cost per byte of the two has entered a platform period,and it is difficult to break through in the next five years.This means that the era of improving performance and reducing costs simply by"shrinking"has come to a substantial end for technologies such as SRAM.
 

Why 2D scaling doesn't work for SRAM?

Traditional two-dimensional(2D)semiconductor scaling has made great strides,constantly pushing up the storage density.But now,both SRAM and DRAM have hit the double"south wall"of physics and economy.For SRAM,its core limitation has reached the physical limit.SRAM cell is usually composed of six transistors,and its structure is precise.When the size of the transistor is reduced to the atomic scale,the slight deviation in manufacturing will lead to the performance mismatch of the transistor in the cell,which will seriously weaken its signal stability and reliability.To put it simply,it is not that we can't make SRAM smaller,but that it may not work stably after it is made smaller.This is different from the logic circuit,which can correct errors through signal regeneration,and once the SRAM cell goes wrong,the data will be lost.
 

This bottleneck leads to a direct consequence:it is difficult for the cell size and cost of SRAM to linearly decrease with the process progress.The capacity growth of on-chip cache(mainly composed of SRAM)is seriously limited by the chip area at first.Looking at the server CPU(such as AMD EPYC processor)which is often hundreds or even thousands of square millimeters,it is unrealistic in economy and heat dissipation to continue to expand the chip area indefinitely to pile SRAM cache.
 

Contrast:The Dilemma of DRAM and the Similarity and Difference of SRAM

In contrast,the bottleneck of DRAM is more from the complex manufacturing process.Its core is tiny capacitance,which requires extremely deep high aspect ratio etching technology to ensure charge storage,and the transistor structure becomes complicated in order to reduce leakage.The more advanced the process,the more difficult and costly these steps are,which leads to the flattening of the cost per bit curve of DRAM.Although the causes of the dilemma of SRAM and DRAM are different(SRAM focuses on physical limits,while DRAM focuses on process costs),the results are similar:the decline rate of storage costs has been far behind the evolution rate of logic chips.In the total system cost,the proportion of memory(especially DRAM)and cache(SRAM)is becoming higher and higher.
 

Way out:from"heap capacity"to"improving efficiency"

Facing the end of 2D scaling of SRAM and DRAM,the focus of the industry must shift from"how to make cheaper and larger memory"to"how to use existing memory resources more intelligently and efficiently".

Specific directions include:

1.Architecture innovation:adopting smarter cache hierarchy,NUMA optimization,and a subversive scheme like AMD 3D V-Cache,which greatly increases the SRAM cache capacity through 3D stacking technology without significantly increasing the chip area.
 

2.Software and algorithm optimization:Through compiler optimization,data prefetching algorithm and memory access mode optimization of the application itself,the hit rate and data reuse rate of SRAM cache can be improved,so that every KB of expensive cache can be fully utilized.
 

3.Heterogeneous integration:Explore the integration of different types of memories(such as eMRAM and other new nonvolatile memories)with SRAM and logic core to build a more efficient storage subsystem.