SRAM technology and density expansion

In the semiconductor storage system,SRAM has long occupied the core position of cache and on-chip storage with its fast response and high stability.However,as the process nodes continue to explore,the physical limits of traditional planar transistors are pushing the development of SRAM into a new stage full of challenges.
 

Looking back at the era of planar transistors,every process node progress can significantly improve the SRAM storage density.This is due to the effectiveness of Dennard's scaling law-the transistor size is reduced and the power consumption density remains constant.However,when the process entered the deep nanometer scale,this golden rule gradually failed.
 

The most difficult challenge is that the subthreshold leakage current is out of control.When the transistor should be completely turned off in theory,there is still a weak current between the source and the drain.With the shortening of gate length,the channel control ability is weakened and the leakage current increases exponentially.This not only leads to the soaring static power consumption,but also aggravates the process variability of transistors.In SRAM cells,if the electrical characteristics of transistors constituting bistable latches are mismatched due to variation,it will directly weaken the stability of data retention and even lead to bit errors.

Facing the physical wall,the industry is exploring ways to break the situation along two main lines.
 

The first path is the fundamental change of transistor structure.Complementary FET architecture stacks NMOS and PMOS vertically instead of the traditional side-by-side layout.This three-dimensional integration can greatly reduce the plane area occupied by key circuits,so that SRAM cells can achieve more compact layout design without reducing the size of single tube,and indirectly improve the storage density.
 

The second path is more radical,that is,exploring new storage principles.Magnetoresistive RAM and ferroelectric RAM use magnetic tunnel junctions or polarization inversion of ferroelectric materials to store data,which are non-volatile and have far greater theoretical miniaturization potential than SRAM.Once a breakthrough is made in reading and writing speed and process compatibility,they will bring a leap in inter-generational density for on-chip storage.