Synchronous SRAM with burst characteristics

In computer systems,SRAM(Static Random Access Memory)is widely used in Cache.Cache is a storage unit with small capacity but extremely fast access speed,which is mainly used to temporarily store recently frequently used instructions or data from main memory(usually dynamic memory with slow access speed).The design idea is that the cache controller"predicts"the slow dynamic storage area that the CPU may need to access next,and calls the corresponding data into the cache in advance so that it can be read quickly when necessary.
 

Unlike asynchronous SRAM,synchronous SRAM's working timing is consistent with the system clock.For example,in some systems,the clock signal of synchronous SRAM is exactly the same as that of microprocessor,so that the microprocessor and the memory can realize synchronous transmission at a high speed.The core feature of synchronous SRAM is its clock synchronization mechanism.Taking a simplified 32k×8 memory as an example,its internal structure is similar to asynchronous SRAM in memory array,address decoder,read-write control and enable input,but the key difference is that synchronous SRAM introduces a clock register.All input signals,including address,read-write control,chip enable and input data,are latched into the corresponding registers on the edge of valid clock pulses,and the memory operation after latching is completely synchronized with the system clock.
 

According to the different data output modes,synchronous SRAM can be divided into two basic types:circulation type and pipeline type.The flow-through synchronous SRAM does not contain a data output register,and the output data is directly sent to the data I/O line in an asynchronous manner through the output buffer;The pipeline synchronous SRAM is provided with a data output register,and the output data is stably sent to the data I/O line under the control of clock synchronization,thus realizing more efficient pipeline operation.
 

Synchronous SRAM usually has the feature of address Burst,which allows the memory to read and write four address cells continuously through only one external address.Specifically,when the external address is latched into the address register,the burst logic circuit will use the least two addresses A0 and A1 to generate the combination of 00,01,10 and 11 in turn under the drive of continuous clock pulses,thus generating four sequential address sequences including the original external address internally,effectively improving the efficiency of continuous data access.