SRAM scalability bottleneck

In almost all computing devices,program codes and running data are stored in SRAM.The processor reads instructions from the SRAM,and then operates the data also located in the SRAM according to the instructions.Compared with the registers that temporarily store data in the processor,the cost of SRAM is lower-although the registers can be realized with the same number of transistors,their decoding and access mechanisms are more expensive,and they cannot be effectively expanded with the increase of the number of registers.
 

SRAM itself consists of a large number of memory cells,and the periphery is surrounded by auxiliary circuits for random reading and writing of data.In many designs,these peripheral circuits are semi-customized and will be adjusted with the change of storage array size.Interestingly,the improvement of SRAM speed in recent years comes more from the optimization of peripheral circuits than from the improvement of memory cells themselves.
 

What is really worrying,however,is that with the shrinking of process nodes,SRAM with the same capacity accounts for more and more of the total chip area.In other words,the capacity and performance of SRAM are almost stagnant,while the logic part is still moving forward,and the gap between them is widening.
 

When more and more chips touch the physical limit of lithography equipment,this imbalance becomes unbearable.Chip designers have to rely on external memory more frequently than before.However,the access speed of external memory is much lower than that of on-chip SRAM,which will directly drag down the overall computing performance and bring additional complexity to the system architecture.