Why SRAM miniaturization has stagnated?

With the continuous advancement of semiconductor technology,the shrinking speed of SRAM(Static Random Access Memory)has obviously slowed down,and it can even be said that it has come to a standstill.Many chip design teams have found that the size of transistors can continue to shrink,but the size and performance of SRAM cells no longer benefit synchronously.The reason behind this is not complicated.
 

The initial design goal of SRAM bit cell is clear:to achieve high-density storage with the smallest area.However,there is a long-tolerated defect in the 6T structure-the requirements for transistors in read operation and write operation are opposite.There is a subtle competition between access tube and storage tube,which needs to be carefully balanced and process deviation should be taken into account.With the geometric size getting smaller and smaller,the influence of process fluctuation on the reading and writing characteristics of bit cells is getting higher and higher,and the deviation that could have been ignored is now the main contradiction.
 

At the more advanced process node,electrostatic control and random doping fluctuation become the two core constraints,which directly prevent the cell area from shrinking according to the expected proportion.At the same time,the wire resistance and bit line parasitic capacitance not only did not decrease,but increased,which made the access speed of SRAM hit the bottleneck ahead of time.Even more embarrassing,the power supply voltage Vdd has hardly decreased in recent generations of processes.Logic circuits can continue to be miniaturized through device structure innovation and wiring skills,but it is difficult for SRAM to find the same space.
 

When SRAM can no longer expand freely,large register files and multilevel cache hierarchy are naturally limited.This directly aggravates the pressure on chip area,yield,power consumption efficiency and data transmission efficiency.An obvious change is that the bottleneck is shifting from computing density to memory architecture and interconnection efficiency.
 

This means that the software layer must adjust the past assumptions-the future memory hierarchy will be more complex,and the speed difference between levels will be more dispersed.Data locality,block processing,partition management and predictability of access flow will become more and more important.The delay difference between different levels will be the key factor to limit the system-level performance of SRAM.