Manufacture of SRAM under advanced FinFET process

In current CMOS logic integrated circuits, static random access memory (SRAM) has become the mainstream choice of cache memory cells because of its high-speed reading and writing ability. A typical SRAM cell consists of two latch inverters and two transmission NMOS transistors, one of which is connected to the bit line, and the other is connected to the opposite bit line, which together form a six-transistor structure, including four NMOS and two PMOS. Compared with a DRAM cell that only needs one NMOS and one capacitor, or a NAND flash memory cell composed of a single device, the number of transistors in SRAM is obviously more. This also leads to the fact that SRAM usually bears the highest graphic density in logic CMOS chips and is often used as a test and verification carrier in the development of new generation process nodes.
 

With the advancement of advanced manufacturing process, the SRAM array integrated with modern CMOS logic chips can reach 250 million cells. Take Figure 3.24(a) as an example, which shows only a small array with only 24 cells. To construct SRAM based on FinFET technology, at least four doped layers are needed: n-well, p-well, n-type source-drain layer (n-S/D) and p-type source-drain layer (p-S/D). If the back gate high k metal gate (HKMG) structure is adopted, an NMOS metal gate (MG) mask layer needs to be added additionally. The function of this mask layer is to form the work function metal gate of NMOS by removing the work function metal layer of PMOS or the MG barrier layer of PMOS. In fact, with the help of chemical reaction, PMOS work function metal can also be transformed into NMOS work function metal, thus flexibly regulating the threshold voltage.
 

In order to continue to miniaturize the FinFET process to 7 nm or even 5 nm nodes, engineers usually start from two directions: one is to increase the fin height and improve the pattern density, and the other is to introduce extreme ultraviolet (EUV) lithography technology or self-aligned quadruple pattern (SAQP) multiple cutting process. At the same time, new semiconductor materials have begun to replace traditional silicon fins, such as silicon germanium (SiGe), pure germanium (Ge) and III-V compounds such as indium gallium arsenic (InGaAs). These materials can significantly improve the carrier mobility in the channel, thus maintaining the performance and stability of SRAM cells in a smaller size.