Why is SRAM fast and does not need to be refreshed?

The memory cell of SRAM does not depend on the dynamic maintenance of capacitor charge,but is a logic self-locking structure based on bistable flip-flop.A typical design uses six transistors(6T architecture)to form a positive feedback loop,which has two stable states corresponding to logic levels"0"and"1"respectively.Under the condition of constant power supply,this loop can maintain its current state indefinitely without the intervention of background refresh operation.This level holding method fundamentally eliminates the risk of data loss caused by charge leakage,and the state switching is completely completed directly by transistor switching action,and there is no time delay in capacitor charging and discharging,so its reading and writing cycle can be compressed to several nanoseconds,which is enough to closely follow the core clock frequency of modern CPU.
 

SRAM has very low static leakage current and excellent static power consumption control in standby or data retention state.However,during high-frequency reading and writing operations,the frequent parasitic capacitances of bit lines and word lines charge and discharge,which will lead to a significant increase in dynamic power consumption.Therefore,in SoC design,the working frequency and power management strategy of SRAM array are usually balanced to optimize the overall energy efficiency ratio.