What is SRAM and how is it different from existing HBM solutions?

Static random access memory(SRAM)is the basic storage component in the internal cache system of the processor.Different from dynamic random access memory(DRAM),SRAM has a latch structure with multiple transistors for each storage bit,which can maintain the written binary data state without periodic refresh.As long as the power supply voltage is stable,the logic level will remain valid until it is overwritten by a new write operation.
 

High-bandwidth memory(HBM)uses TSV silicon through-hole technology to vertically stack multiple DRAM dies and interconnect them with logic chips through micro bumps.At present,the mass production scheme generally stacks 12 to 16 layers,and the capacity of a single stack can reach more than 16GB.However,the access delay of HBM is usually in the range of 50-100 nanoseconds,while the read delay of SRAM is only about 1-3 nanoseconds,and there is an order of magnitude gap between them.The ultra-low delay of SRAM comes from the fact that it is on the same silicon substrate as the computing unit,and the signal transmission path is extremely short,and there is no need to go through a complex memory controller scheduling queue.In terms of power consumption,the dynamic energy consumption of SRAM per bit read and write operation is significantly lower than that of HBM,because the latter needs to drive long inter-chip interconnection lines and maintain the refresh current of DRAM cells.
 

The core bottleneck of SRAM is the storage capacity per unit area.Under the same process node,the physical size of SRAM cell is about 5 to 6 times that of DRAM cell,which means that the number of memory bits that SRAM can integrate is only about one-fifth of that of DRAM in the same chip area.With the vertical stacking architecture,HBM achieves more than 80 times the capacity advantage in a similar footprint,which is very important for large-scale data set loading and matrix operations.However,it must be pointed out that the bandwidth improvement of HBM mainly depends on wide bit width parallel transmission(typical bit width is 1024 bits),rather than the sharp jump of single pin rate,so its data throughput is limited by parasitic parameters of interconnection lines and synchronous clock frequency.
 

SRAM and HBM are not substitutes,but serve two different levels of low latency cache and high throughput memory in the computing system.The selection should be weighed according to the characteristics of workload-frequently accessed hot data is preferentially deployed in SRAM,while the bulk data is moved by HBM,which together constitute the storage layer cornerstone of modern high-performance computing chips.