Structure and working principle of SRAM cell

A typical SRAM memory bit adopts a six-transistor(6T)symmetrical layout,which achieves an excellent balance between area efficiency and stability.Its core consists of a pair of cross-coupled CMOS inverters,forming a bistable latch structure.This pair of inverters(composed of four transistors)are locked with each other,which ensures that the data of the storage node is continuously stable under static conditions and is not affected by time decay.
 

Two additional NMOS transistors are used as access control switches to connect the internal latch node with external Bitlines.The whole cell is arranged in 2x2 grid logic.The word line(WL)drives the gate of the access tube horizontally,while the complementary bit lines(BL and BL')extend vertically,which is used for differential signal transmission,effectively suppressing common-mode noise and improving reading reliability.
 

Compared with DRAM which needs to refresh capacitor charge periodically,the 6T cell structure of SRAM gives it two significant advantages:first,it does not need refresh logic,which simplifies the peripheral control circuit;Second,the static power consumption is extremely low and the read-write access time is extremely short.For this reason,although the density per unit area of SRAM chip is lower than that of DRAM,it is still an irreplaceable choice in memory subsystems with strict requirements on delay and bandwidth(such as level 1/level 2 cache).