SRAM Core Operation Mode: Hold, Read and Write

SRAM (Static Random Access Memory) occupies a core position in cache, embedded system and network processor, the key lies in its unique cell structure and operating mechanism. Unlike traditional DRAM, which needs periodic refresh, SRAM relies on a latch consisting of six transistors (typical 6T structure) to maintain data. As long as the power supply is not interrupted, the storage state will remain stable. This static characteristic gives it the advantages of low delay and high reliability, but at the same time it also makes its unit area larger and its cost relatively higher. In practical work, SRAM cells switch around three basic states: data holding, data reading and data writing. The three work together to ensure accurate and efficient information access.
 

1, keep the state

When the word line (WL) is at the low level, both access transistors are in the off state, and the electrical path between the storage node and the bit line (BL/BLB) is completely cut off. At this time, a pair of cross-coupled inverters in the cell form a positive feedback closed loop-if the node Q is high, the inverted QB is low, which in turn consolidates the high level of Q and forms self-locking. Even if the external bit line is disturbed, this internal regenerative structure can restrain the noise within the tolerance range and only produce very low static leakage current. This is the physical root of SRAM without background refresh operation.
 

2. Read operation

SRAM read operation relies on sensitive differential detection mechanism. The precharge circuit first equalizes the two bit lines to the power supply voltage (VDD), then activates the word line and turns on the access transistor. Because of the different potentials of SRAM storage nodes, there is a slight difference in the conduction ability between the two access tubes: when one node is "0", the corresponding bit line will discharge to ground through the pull-down path, resulting in a slight drop in the bit line voltage; While that bit line on the other side basically maintain a high level. This difference may be only a few hundred millivolts, but the high-gain differential sense amplifier can amplify this weak signal to logic level standard in a very short time and complete data interpretation. The whole reading process does not destroy the original state of the latch, which belongs to non-destructive reading, and the cell contents are still intact after reading.
 

3. Write operation

The writing operation of SRAM is essentially forced to flip the latch state, which needs to overcome the self-holding force of inverter. After the word line is turned on, the write driver applies opposite full-amplitude voltages to the bit line pair-for example, when writing a "0", pull BL to ground and BLB to VDD. This strong driving signal passes through the access tube to the internal node, and its current is enough to overwhelm the maintenance strength of the original feedback loop, forcing the latch state to flip. After the new steady state is established, the bit line drive is cancelled, and the cross-coupling structure locks the new data immediately to complete the writing.