What is the peripheral circuit of SRAM?

When it comes to SRAM,most people first think of the classic 6T memory cell.However,in the real SoC and CPU design,it is often not the Cell itself that determines the SRAM area,power consumption and access speed,but the Peripheral Circuit around the memory array.A complete SRAM read/write operation is followed by multi-step cooperative actions such as address decoding,bit line precharge and differential amplification.
 

1.Row decoding and column decoding:translate the address into the selected signal.

SRAM array is arranged in two-dimensional matrix,and the input address needs to be divided into two parts:row address and column address.Row Decoder is responsible for translating the N-bit row address into a word line(WL)driving signal,selecting only one row from 2 N rows,and opening the access tubes of all memory cells on the corresponding row.
 

The Column Decoder works with the multiplexer(MUX)to select the target bit from hundreds of columns,and then send the data to the subsequent read-write port.Because modern SRAM arrays often reach the scale of several Mb or even tens of Mb,the decoding tree itself will consume considerable layout area and dynamic power consumption,so the fan-out control and timing reconstruction of the decoder have always been the focus of SRAM compiler optimization.
 

2.Pre-charge circuit:Let the bit line be at the initial level of"readable"

The SRAM read operation depends on the slight voltage difference between the bit line BL and its inverted phase line BLB.Before the start of the read cycle,the Precharge Circuit will simultaneously pull BL and BLB to a level close to VDD,so that the two bit lines are at the common-mode starting point.If this step is omitted,the residual random charge on the bit line will make the sense amplifier unable to judge the differential direction,and the reading operation will fail directly.
 

3.Sense amplifier:the core module that determines the delay of SRAM Cache.

In the actual SRAM reading process,the voltage difference generated by the memory cell pulling/pulling on the bit line through the access tube is usually only a few tens of millivolts.For a high-frequency CPU,it is slow and unreliable to directly sample such a weak signal,so it is necessary for a sense amplifier(SA)to identify the differential direction within a sub-nanosecond time window and amplify it to a full swing digital level.
 

The response speed and offset voltage of SA basically determine the access delay and yield of SRAM Cache.With the process node pushing below 28nm,the VDD is decreasing and the parasitic capacitance of bit line is increasing,and the design margin of SA is getting narrower and narrower,which has become the most sensitive module in the whole SRAM macro and needs repeated simulation and optimization.